1. Field of the Invention
The present invention relates to a display control method and apparatus for liquid crystal display device in which a ferroelectric liquid crystal (hereinafter abbreviated as FLC) is used.
2. Description of the Prior Art
FIG. 1 is a sectional view showing a schematic configuration of an FLC panel. Two sheets of glass substrates 5a, 5b are disposed in opposition to each other. A signal electrode S consisting of indium tin oxide (hereinafter abbreviated as ITO) is arranged plurally in parallel on the surface of one glass substrate 5a, and further, its surface is covered by a transparent insulating film 6a consisting of SiO.sub.2. On the surface of the other glass substrate 5b apposing to the signal electrode S, a scanning electrode L consisting of ITO is arranged plurally in parallel in a direction orthogonal to the signal electrode S, and covered by a transparent insulating film 6b consisting of SiO.sub.2. On the insulating films 6a, 6b, orientation films 7a, 7b consisting of polyvinyl alcohol and treated by rubbing processing are formed respectively.
The two glass substrates 5a, 5b are bonded together with a sealing agent 8 partially leaving an injection port, which is sealed by the sealing agent 8 after the FLC 9 is introduced into a space between the orientation films 7a, 7b by the vacuum injection therethrough. The two glass substrates 5a, 5b thus bonded together are clamped between two polarizing plate 10a, 10b which are arranged such that respective polarizing axes intersect orthogonally.
FIG. 2 is a block diagram schematically showing a configuration of display device using the aforesaid FLCD 1. In the display device information necessary for the image display is obtained from a digital signal outputted to a CRT display 3 from a personal computer 2. The digital signal is transformed into a drive signal for displaying images on the FLCD 1 in a control circuit 4, (illustrated in FIG. 6) and the image display on the FLCD 1 is effected by the drive signal.
FIG. 3 and FIG. 4 are plan views showing the configuration of an FLC display (hereinafter abbreviated as FLCD) 1, in which a scanning side driving circuit 11 is connected to the scanning electrode L of the FLCD 1 having a simple matrix configuration aforementioned, and a signal side driving circuit 12 is connected to the signal electrode S. The scanning side driving circuit 11 is a circuit for applying voltages to the scanning electrodes L, and the signal side driving circuit 12 is a circuit for applying voltages to the signal electrodes S.
Here, for the purpose of simplification, the case wherein a number of the scanning electrodes L are 32 and a number of the signal electrodes S are 16, or the case of FLCD 1 constituting by picture elements of 32.times.16 is shown, and respective electrodes of the scanning electrodes L are distinguished by adding an index i (i=1 to 32), to the symbol L, and respective electrodes of the signal electrodes S are distinguished by adding an index j (j=1 to 16) to the symbol S. In the description made hereinafter, a picture element at intersection of any scanning electrode Li and any signal electrode Sj is represented by a symbol Aij.
FIG. 5 is a waveform diagram of signals outputted from the personal computer 2 to the CRT display 3 above-mentioned. FIG. 5 (1) is a horizontal synchronizing signal HD- which gives the period of one horizontal scanning interval of image information outputted to the CRT display 3, FIG. 5 (2) is a vertical synchronizing signal VD- which gives the period of one picture screen of the information, and FIG. 5 (3) shows the information as display data Data for every horizontal scanning interval in the lump, index numerals corresponding to the scanning electrode Li of the FLCD 1.
FIG. 5 (4) is a waveform diagram showing an expanded one horizontal scanning interval of the horizontal synchronizing signal HD-, FIG. 5 (5) is a waveform diagram showing an expanded one horizontal scanning interval of the display data Data, index numerals corresponding to the signal electrode Sj of the FLCD 1, and FIG. 5 (6) is a waveform diagram showing a data transfer clock CLK of the display data Data for every picture element.
FIG. 6 is a block diagram schematically showing a configuration of the control circuit 4. A display memory 16 is for storing display data Data of one picture screen outputted from the personal computer 2 of FIG. 2. From the display memory 16, transformation data Rx showing the difference between the display data displayed, at present, on the picture screen of the FLCD 1 and the display data to be displayed in the next frame is outputted to a discriminating memory 17 and a reference memory 18, and display data Do to be displayed in the next frame is outputted to a drive control circuit 19.
The discriminating memory 17 stores, in response to the transformation data Rx outputted from the display memory 16, whether or not there is even one picture element on the scanning electrode of the FLCD 1 where the display data displayed at present differs from the display data to be displayed in the next frame, as discrimination data for every scanning electrode. In the discriminating memory 17, one-bit memory capacity is allocated respectively to hold the discrimination data for every scanning electrode, and outputted to the output control circuit 14 as discrimination data SAME-. The reference memory 18 stores the transformation data Rx of one picture screen outputted from the display memory 16 as it is.
An input control circuit 13 is the circuit which, in response to the horizontal synchronizing signal HD-, vertical synchronizing signal VD- and clock CLK outputted from the personal computer 2, controls the input side operation of the display memory 16, discriminating memory 17 and reference memory 18 directly or indirectly through an input/output switching circuit 15.
The output control circuit 14 is the circuit which, in response to the discrimination data SAME- outputted from the discriminating memory 17 and an internal clock CK, controls the output side operation of the display memory 16, discriminating memory 17 and reference memory 18 directly or indirectly through the input/output switching circuit 15, and at the same time, indicates the display position of display data DATA outputted from the drive control circuit 19 on the FLCD 1.
The input/output switching circuit 15 is the circuit which, in response to the signals of the input control circuit 13 and the output control circuit 14, switches the input/output timing of the display memory 16, discriminating memory 17 and the reference memory 18.
The drive control circuit 19 is the circuit which outputs image data DATA on the basis of the display data Do given from the display memory 16 and difference data Dre given from the reference memory 18, and in response to the signal given from the output control circuit 14, outputs the signal giving a display position of the image data DATA on the FLCD 1, a selective voltage VCa, a non-selective voltage VCb, a non-rewriting voltage VSg, a dark rewriting voltage VSd and a bright rewriting voltage VSe to the FLCD 1.
FIG. 7 and FIG. 8 are specific voltage waveforms of the selective voltage VCa and non-selective voltage VCb applied to the scanning electrode L, and the non-rewriting voltage VSg, dark rewriting voltage VSd and bright rewriting voltage VSc applied to the signal electrode S. Waveforms shown in FIG. 7 (1) and FIG. 8 (1) are of the selective voltage VCa which is applied to the scanning electrode L for rewriting the memory state of the picture elements on the scanning electrode L, or the luminous state displayed, and waveforms shown in FIG. 7 (2) and FIG. 8 (2) are the non-selective voltage VCb which is applied to the other scanning electrodes L for not rewriting the display state of the picture elements thereon. Waveforms shown in FIG. 7 (5) and FIG. 8 (5) are of the non-rewriting voltage VSg which is applied to the signal electrode S for not rewriting the display state of the picture elements on the scanning electrode L to which the selective voltage VCa is applied, waveforms shown in FIG. 7 (4) and FIG. 8 (4) are of the dark rewriting voltage VSd which is applied to the signal electrode S for rewriting the display state of the picture elements on the scanning electrode L to which the selective voltage VCa is applied into a "dark" luminous state and waveforms shown in FIG. 7 (3) and FIG. 8 (3) are of the bright rewriting voltage VSc which is applied to the signal electrode S for rewriting the display state of the picture elements on the scanning electrode L to which selective voltage VCa is applied, into a "bright" luminous state.
FIG. 7 (6) to FIG. 7(11) and FIG. 8 (6) to FIG. 8 (11) respectively show waveforms of the effective voltage applied to the picture element Aij. A waveform A-G of FIG. 7 (8) and FIG. 8 (8) shows the voltage waveform applied to the picture element Aij, when the selective voltage VCa is applied to the scanning electrode Li and the non-rewriting voltage VSg is applied to the signal electrode Sj, a waveform A-D of FIG. 7 (7) and FIG. 8 (7) shows the voltage waveform applied to the picture element Aij, when the selective voltage VCa is applied to the scanning electrode Li and the dark rewriting electrode VSd is applied to the signal electrode Sj, a waveform A-C of FIG. 7 (6) and FIG. 8 (6) shows the voltage waveform applied to the picture element Aij, when the selective voltage VCa is applied to the scanning electrode Li and the bright rewriting voltage VSc is applied to the signal electrode Sj, a waveform B-G of FIG. 7 (11) and FIG. 8 (11) shows the voltage waveform applied to the picture element Aij, when the non-selective voltage VCb is applied to the scanning electrode Li and the non-rewriting voltage VSg is applied to the signal electrode Sj, a waveform B-D of FIG. 7 (10) and FIG. 8 (10) shows the voltage waveform applied to the picture element Aij, when the non-selective voltage VCb is applied to the scanning electrode Li and the dark rewriting voltage VSd is applied to the signal electrode Sj, and a waveform B-C of FIG. 7 (9) and FIG. 8 (9) shows the voltage waveform applied to the picture element Aij, when the non-selective voltage VCb is applied to the scanning electrode Li and the bright rewriting voltage VSc is applied to the signal electrode Sj.
FIG. 9 and FIG. 10 are waveform diagrams showing drive signal outputted to the FLCD 1 from the control circuit 4, in case the display state of the picture elements Aij of the FLCD 1 is rewritten from Japanese characters meaning "FERROELECTRIC" shown in FIG. 4 to Japanese Characters meaning "ORDINARY DIELECTRIC" shown in FIG. 3 by using the control circuit 4 of FIG. 6 aforementioned. FIG. 9 (2) and FIG. 10 (2) are waveform diagrams showing a selective signal YI for selecting the scanning electrode Li, FIG. 9 (1) and FIG. 10 (1) are waveform diagrams showing the clock YCK- for sequentially transferring the selective signal YI in a shift register, not shown, included in the scanning side during circuit 11, FIG. 9 (4) and FIG. 10 (4) are waveform diagrams showing the clock LCK- which takes in and holds the selective signal YI in a shift register, not shown, included in the same scanning side driving circuit 11, and FIG. 9 (3) and FIG. 10 (3) show display data DATA corresponding to the picture elements of the FLCD 1, index numerals corresponding to the scanning electrodes Li of the FLCD 1.
FIG. 9 (5) is a waveform diagram showing the expanded clock YCK- for one selective time, FIG. 9 (6) is a waveform diagram showing the expanded selective signal YI for one selective time, and FIG. 9 (7) is a waveform diagram showing the expanded display data DATA for one selective time, index numerals corresponding to the signal electrodes Sj of the FLCD 1.
FIG. 9 (8) is a waveform diagram showing a data transfer clock XCK for sequentially transferring the display data DATA in a shift register, not shown, included in the signal side driving circuit 12, FIG. 9 (9) is a waveform diagram showing a latch pulse LP which gives timing for taking in and holding simultaneously the display data DATA in a shift register, not shown, included in the signal side driving circuit 12, in a separate shift register, not shown, included in the signal side driving circuit 12, FIG. 9 (10) is a waveform diagram schematically showing voltages VCa, VCb applied to the scanning electrode L, and FIG. 9 (11) is a waveform diagram schematically showing voltages VSc, VSd, VSg applied to the signal electrode S. FIG. 10 (1) to FIG. 10 (4) show waveforms following the waveforms of FIG. 9 (1) to FIG. 9 (4).
The conventional driving method will be described along the waveform diagrams shown in FIG. 9 and FIG. 10. In a frame in which Japanese characters meaning "FERROELECTRIC" are shown on the picture screen of the FLCD 1, display data Do stored in the display memory 16 are the state of picture elements of 32.times.16 in FIG. 4 itself, and discrimination data stored in the discriminating memory 17 are all brought to "0".
Since the display data Data displaying Japanese characters meaning "ORDINARY DIELECTRIC" is sent to the display memory 16 from the personal computer 2 in this state, from the display memory 16, transformation data Rx of one picture screen which is the difference between "FERROELECTRIC" and "ORDINARY DIELECTRIC" and shown schematically in FIG. 11, is sent to the discriminating memory 17 and the reference memory 18. Though the transformation data Rx is held as it is in the reference memory 18, the transformation data Rx for one scanning electrode are held in the lump in the discriminating memory 17. That is, "1" is held from the scanning electrodes L1 to L16, and "0" is held from the scanning electrodes L17 to L32.
Waveforms in FIG. 9 and FIG. 10 explain the operation thereafter. The output control circuit 14 outputs an output side line address OAc "1" to the display memory 16, discriminating memory 17 and reference memory 18 through the input/output switching circuit 15, and checks discrimination data SAME- which is the output signal of the discriminating memory 17. As described above, since the value of discrimination data corresponding to the scanning electrode L1 is "1", output side row addresses OAs "1" to "4" are outputted to the display memory 16 and the reference memory 17, display data Do and difference data Dre corresponding to the scanning electrode L1 are outputted to the drive control circuit 19, and the value of discrimination data corresponding to the scanning electrode L1 of the discriminating memory 17 is returned to "0".
The drive control signal 19 outputs the "dark rewriting" signal to the signal side driving circuit 12 of the FLCD 1 as display data DATA, when the display data Do is "dark" and the difference data Dre is "change", outputs the "bright rewriting" signal as display data DATA when the display data Do is "bright" and the difference data Dre is "change", and outputs the "non-rewriting" signal as display data DATA when the display data Do is "bright" or "dark" and the difference data Dre is "same".
Though the output control circuit 14 then outputs the output side line address OAc "2", the control circuit 4 repeats the aforesaid operations till the output side address OAc becomes "17".
When the output control circuit 14 outputs the output side line address OAc "17" and check discrimination data SAME- which is the output signal of the discriminating memory 17, since the value of discrimination data corresponding to the scanning electrode L17 is "0", the output control circuit 14 rechecks discrimination data SAME-designating the output side line address OAc as "18". Though the operations are repeated up to four times, whenever the output control circuit 14 outputs the output side line address OAc "20", regardless of the value of discrimination data SAME- which is the output signal of the discriminating memory 17, the output side row address OAs is outputted to the display memory 16 and the reference memory 17, the display data Do and difference data Dre are outputted to the drive control circuit 19, and the value of discrimination data of the discriminating memory 17 corresponding to the scanning electrode L1 is returned to "0".
The drive control circuit 19 outputs the display data DATA to the signal side driving circuit 12 of the FLCD 1 in the basis of the display data Do and difference data Dre as described above.
Though the operation is repeated hereinafter, when image information outputted from the personal computer 2 has changed while repeating the operation, in accordance with the change the stored contents of the display memory 16, discriminating memory 17 and reference memory 18 will change similarly to the case wherein the image information has changed from "FERROELECTRIC" to "ORDINARY DIELECTRIC" aforementioned. In the discriminating memory 17, the discrimination data which was "1" at that time does not change but remains as "1".
Though display data DATA is inputted to the signal side driving circuit 12 in such a matter, in the signal side driving circuit 12, the display data DATA is sequentially transferred in the shift register, not shown, by the data transfer clock XCK, and taken into the separate register, not shown, in synchronism with the latch pulse LP. When the value of display data DATA taken into the register is "dark rewriting" the dark rewriting voltage VSd is applied to the corresponding signal electrode, when the value of display data DATA is "bright rewriting" the bright rewriting voltage VSc is applied to the corresponding signal electrode, and when the value of display data DATA is "non-rewriting" the non-rewriting voltage VSg is applied to the corresponding signal electrode.
For indicating the scanning electrode corresponding to the display data DATA taken into the register aforementioned, the selective signal YI and clock signals YCK-, LCK- are outputted from the drive control circuit 19.
In the scanning side driving circuit 11, the selective signal YI is sequentially transferred in the shift register, not shown, included in the scanning side driving circuit 11 by the transfer clock YCK-, and taken into the separate register, not shown, included in the scanning side driving circuit 11 in synchronism with the hold clock LCK-. When the value of the selective signal YI taken into the register is "1" the selective voltage VCa is applied to the corresponding scanning electrode, and when the value of the selective signal YI is "0" the selective voltage VCb is applied to the corresponding scanning electrode.
According to such conventional driving method, for the picture elements on the scanning electrode whose display data displayed at present and the display data in the next frame is same, since only the non-rewriting voltage is applied to the signal electrode even when the scanning electrode is not selected or selected, it is possible to display without flickers by rewriting the picture elements even when the number of scanning electrodes of the FLCD is increased.
Such a conventional driving method has been proposed in Japanese Patent application Laid Open No. sho 64-59389 (1989), and as the impressed voltage waveforms to the scanning electrode L and the signal electrode S used usually in the driving method of the FLCD 1, explained by the waveform diagram shown in FIG. 12 in place of FIG. 7 and FIG. 8. A waveform shown in FIG. 12 (1) is the waveform of a selective voltage A which is applied to the scanning electrode L, and is able to rewrite the memory state of the picture elements on the scanning electrode L or the luminous state displayed, and a waveform shown in FIG. 12 (2) is the waveform of an non-selective voltage B which is applied to the scanning electrode L, but can not rewrite the display state of the picture elements on the scanning electrode L.
A waveform shown in FIG. 12(3) is the waveform of a bright rewriting voltage C which is applied to the signal electrode S when rewriting the picture elements into the "bright" luminous state, a waveform shown in FIG. 12(4) is the waveform of a dark rewriting voltage D which is applied to the signal electrode S when rewriting the picture elements into the "dark" luminous state, and a waveform shown in FIG. 12(5) is the waveform of a non-rewriting voltage G which is applied to the signal electrode S when the display state of the picture elements is not rewritten.
FIG. 12(6) to FIG. 12(11) are waveform diagrams showing waveforms of an effective voltage applied to the picture element Aij. A waveform A-C of FIG. 12(6) shows the waveform when the selective voltage A is applied to the scanning electrode Li and the bright rewriting voltage C is applied to the signal electrode Sj, a waveform A-D of FIG. 12(7) shown the waveform when the selective voltage A is applied to the scanning electrode Li and the dark rewriting voltage D is applied to the signal electrode Sj, a waveform A-G of FIG. 12(8) shows the waveform when the selective voltage A is applied to the scanning electrode Li and the non-rewriting voltage G is applied to the signal electrode Sj, a waveform B-C of FIG. 12(9) shows the waveform when the non-selective voltage B is applied to the scanning electrode Li and the bright rewriting voltage C is applied to the signal electrode Sj, a waveform B-D of FIG. 12(10) shows the waveform when the non-selective voltage B is applied to the scanning electrode Li and the dark rewriting voltage D is applied to the signal electrode Sj, and a waveform B-G of FIG. 12(11) shows the waveform when the non-selective voltage B is applied to the scanning electrode Li and the non-rewriting voltage G is applied to the signal electrode Sj.
In case the display state of the picture elements Aij of the FLCD 1 of FIG. 4 is rewritten by the aforesaid driving method, the selective voltage A shown in FIG. 12(1) is applied to the scanning electrode Li, and the non-selective voltage B shown in FIG. 12(2) is applied to all remaining scanning electrodes Lk(k.noteq.i, k=1 to 32), when the picture elements Aij are rewritten into the "bright" display state, the bright rewriting voltage C shown in FIG. 12(3) is applied to the signal electrode Sj, when the picture elements Aij are rewritten into the "dark" display state, the dark rewriting voltage D shown in FIG. 12(4) is applied to the signal electrode Sj, and when the "bright" display state or the "dark" display state of the picture elements Aij in the preceding frame may be kept as it is, the non-rewriting voltage G shown in FIG. 12(5) is applied to the signal electrode Sj.
For instance, in case the state wherein Japanese characters meaning "FERROELECTRIC" are displayed on the picture screen by the picture elements Aij which are in the "dark" display state shown by oblique lines in the FLCD 1 of FIG. 4, is rewritten into the state wherein Japanese characters meaning "ORDINARY DIELECTRIC" are displayed as shown in FIG. 3, the picture elements Aij which are rewritten from the "dark" display state to the "bright" display state are represented in FIG. 13 by a symbol C corresponding to the bright rewriting voltage C, the picture elements Aij which are rewritten from the "bright" display state to the "dark" display state are represented by a symbol D corresponding to the dark rewriting voltage D, the picture elements Aij which are kept in the "dark" display state as it is are represented by a symbol F and the picture elements Aij which are kept in the "bright" display state as it is are represented by no symbol. Therefore, whole image is indicated in FIG. 3. In this case, the picture elements Aij with symbol F and the picture elements Aij without symbol correspond to the non-rewriting voltage G.
FIG. 14 shows respective voltage waveforms applied then to the scanning electrodes L1, L2, L3, signal electrodes S5, S6 and picture elements A15, A16, A25, A26. FIG. 14(1) shows, as a reference, the waveform of a transfer clock YCLK of the selective signal YI in a shift register in the scanning side driving circuit 11, FIG. 14(2) shows the waveform of the selective signal YI, FIG. 14(3) shows the impressed voltage waveform to the scanning electrode L1, FIG. 14(4) shows the impressed voltage waveform to the scanning electrode L2, FIG. 14(5) shows the impressed voltage waveform to the scanning electrode L3, FIG. 14(6) shows the impressed voltage waveform the signal electrode S5, FIG. 14(7) shows the impressed voltage waveform to the signal electrode S6, FIG. 14(8) shows the effective voltage waveform applied to the picture element A15, FIG. 14(9) shows the effective voltage waveform applied to the picture element A16, FIG. 14(10) shows the effective voltage waveform applied to the picture element A25 and FIG. 14(11) shows the effective voltage waveform applied to the picture element A26.
In the driving method stated above, as it will be understood from the effective voltage of the picture element A16 shown in FIG. 14(9), and the effective voltage of the picture element A26 shown in FIG. 14(11), the voltages applied to the picture elements Aij are substantially equal as long as its display state is not rewritten, regardless of selecting or not selecting the scanning electrode Li. From this fact, even in the case of low-speed driving, wherein the time required from applying the selective voltage A to a certain scanning electrode Li till applying the selective voltage A next to the same scanning electrode Li, or one frame period is longer than 33.3 milliseconds (corresponds to 30 Hz), the display without flickers is possible.
In the FLCD in which the driving method described above can be adopted, as far as the non-selective voltage is applied to the scanning electrode Li, or the selective voltage is applied to the scanning electrode Li but the non-rewriting voltage is applied to the signal electrode Sj, the display state of the picture element which is the intersecting point of the scanning electrode and signal electrode should not change.
However, in the FLCD it is very difficult to obtain an unstable memory state perfectly, and usually, even in the panel display area, depending upon the location the area where the dark memory state is stable and the area where the bright memory state is stable are mixed, therefore, when the non-selective voltage is applied continuously to the scanning electrode and the selective voltage is not applied thereto without controlling the orientation state, the memory states of the picture elements are stabilized respectively and it is difficult to distinguish what is displayed.